The present invention relates to double gated transistors and structures to lower the operating voltage while maintaining stable performance of the double gated transistor.
Background: Power Consumption in Integrated Circuits
As the size of integrated circuits shrink, supply voltages must be scaled also. The reduction in supply voltages also puts pressure on threshold voltages.
The threshold voltage of a field effect transistor (FET) is the voltage where a transistor starts to turn on. When supply voltages (Vdd) were 5 Volts, threshold voltage magnitudes were typically around 1.1V. (That is, the threshold voltage (Vt) of an n-channel insulated gate (nMOS) transistor might be +1.1V, and the Vt of a p-channel (pMOS) transistor might be -1.1V.) Note that the supply voltage is more than the sum of the threshold voltage magnitudes: the threshold voltage of the nMOS transistor (Vtn) is greater than or equal to the magnitude of the threshold voltage of the pMOS transistor (Vtp) plus the magnitude of Vtp combined. This is an important relation for complementary MOS (CMOS) circuits, since otherwise the circuits can have metastable states where neither nMOS nor pMOS transistors are on.
With 3.3V supply voltages, threshold voltage magnitudes of around 0.8V are more typical. However, as supply voltages shrink further, the reduction in threshold voltage creates difficulties. Smaller threshold voltages have a side effect of increased leakage.
One of the most promising ways for the reduction of power is to reduce the supply voltage, which in turn degrades the speed of operation in conventional circuits. To relax this speed lowering problem, threshold voltage lowering is an effective method. This technique, however, causes the increase of leakage current as another source of power dissipation.
Several circuit architectures have been proposed to solve the above problems. Those architectures include multi-threshold CMOS (MTCMOS), variable threshold CMOS (VTCMOS), and double gate driven MOS (DGMOS).
Background: Double-Gate MOS
The circuit structure, the cross-sectional view, and the layout of the DGMOS circuit of Wong and Rigby are shown in FIG. 7. A CMOS inverter circuit with n-well process is used as an example. In the DGMOS circuits, the body of the p-channel MOS transistor is connected both to the voltage supply, Vdd, and to the input node through a diode, D1, and a capacitor, Cb, respectively, whereas in the conventional configuration, the body of the p-channel transistor is directly connected to the voltage supply. The diode D2 shown in FIG. 7 expresses the parasitic diode which exists between the source (p+diffusion) and the body (n-) of the p-channel transistor. When the input signal changes, the body bias of the transistor changes simultaneously. Thus the body bias of the p-channel transistor is controlled by the input signal and hence the threshold voltage, Vt, of the p-channel transistor changes dynamically as a result of the body biasing effect, i.e., large magnitude for Vt for Vin =Vdd and small magnitude for Vt for Vin =0. Sub-threshold leakage current of the p-channel channel transistor can be minimized by this technique. Here the diodes D1 and D2 try to keep the body bias between Vdd-VgP and Vdd+Vg1, where Vg1 and VgP are the cut-in voltage of the diodes D1 and D2, respectively.
In this approach, however, the chip area penalty becomes large. Also, the p-n-p bipolar transistor which consists of the p-channel source (p+) (Vdd), p-channel body (n-), and p-substrate (VbN +GND) turns on, when the p-channel body voltage goes below Vdd-VgP. This situation occurs when the input signal changes abruptly from high voltage to low voltage. This leads to undesirable current flow from the p-channel source (Vdd) to the p-substrate (GND). In addition, the method to reduce sub-threshold leakage current proposed by Wong and Rigby can not be applied to both p-channel and n-channel transistors simultaneously. The reason for this can be illustrated by way of example. If the substrate is a p-substrate, a p-MOS is implemented in an n-well and the body bias of the p-MOS can be controlled. However, if it is desired to control the body bias of an n-MOS on the same substrate, the body must be separated from the p-substrate, the bias of which is kept to ground.
Background: Multi-Threshold CMOS
The threshold voltage is the voltage where the transistor turns on. In a Multi-threshold CMOS (MT-CMOS), the two transistors which make up the CMOS circuit have different threshold voltages. High threshold voltage, Vt, transistors separate the logic block consisting of low Vt transistors from the voltage supply. When the system is in sleep mode, these high Vt transistors separate the logic block from the supply voltage and the internal states of the logic blocks are stored in the latch circuit with high Vt transistors. This reduces the current leak through the parasitic transistor of the low threshold voltage transistor.
Background: Variable-Threshold CMOS
In a variable-threshold CMOS (VT-CMOS), the transistor threshold voltage varies depending on whether the circuit is in sleep mode or in active mode. When the circuit is in sleep mode, the threshold voltage is more than it is when it is in active mode. The threshold voltage of the transistor is controlled by applying body bias from an external circuit. This requires additional circuits beyond the CMOS circuit to generate appropriate body bias.
Innovative Structures
The present application discloses a FET consisting of a gate controlling current flow through the transistor channel, a diode and a capacitor jointly controlling the back-bias of the transistor, and a barrier which electrically isolates the transistor body of one transistor from that of another transistor and from the semiconductor substrate in which the transistor lies.
Advantages of the disclosed methods and structures include low supply voltage and/or high speed operation of circuits.